1. Field of the Invention
The invention relates to a method for manufacturing semiconductors, and in particular to a method for manufacturing shallow trench isolation (STI) regions.
2. Description of the Related Art
It is well known that a device isolation region is used to electrically separate two adjacent devices from each other, thereby preventing an unexpected carrier flow therebetween in a substrate. For example, a typical device isolation region is formed between two field effect transistors (FETs) in a densely-packed IC, such as a DRAM so as to reduce a charge leakage between the FETs. In general, the device isolation region is formed by the LOCOS process. Since the LOCOS process has been increasingly matured, a device isolation structure with low cost and high reliability can be obtained by using the LOCOS process. However, the LOCOS process creates an unexpected stress and a bird's break around the device isolation structure. A device isolation structure with a bird's beak formed by the LOCOS process cannot efficiently insolate two adjacent devices from each other, particularly two adjacent small-small devices.
Due to the poor insulation of the device isolation region formed by the LOCOS process, it is intended to replace the device isolation structure with a scalable shallow trench isolation structure in a high density IC.
In a shallow trench isolation process, a trench is formed in a semiconductor substrate by anisotropic etching, and then the trench is filled with oxide to insulate two adjacent devices from each other, thereby forming a shallow trench isolation region. Since the formed shallow trench isolation structure is scalable and has no bird's beak encroachment as stated in the traditional LOCOS process, the shallow trench isolation process is suitable for the CMOS manufacturing.
FIGS. 1A-1E shows a method for manufacturing shallow trench isolation regions. First, referring to FIG. 1A, a pad oxide layer 102 is formed on a silicon substrate 100 by thermal oxidation, wherein the pad oxide layer 102 is used to protect the surface of the silicon substrate 100. Then, a silicon nitride layer 104 is formed on the pad oxide layer 102 by low pressure chemical vapor deposition (LPCVD).
Referring to FIG. 1B, a photoresist (not shown) is formed on the silicon nitride layer 104 and then the silicon nitride layer 104, the pad oxide layer 102 and the silicon substrate 100 are etched to form trenches 110 and 112 in the silicon substrate 100. After that, the photoresist is removed.
Referring to 1C, a liner oxide layer 114 is formed on the inner surfaces of the trenches 110 and 112 by high-temperature thermal oxidation, wherein the liner oxide layer 114 extends to the top corners 120 of the trenches 110 and 112 to contact the pad oxide layer 102. Subsequently, the trenches 110 and 112 are filled with an insulator 116, such as a silicon oxide layer, by atmospheric pressure chemical vapor deposition (APCVD).
Referring to FIG. 1D, excessive part of the insulator 116 is removed by chemical mechanical polishing until the surface of the silicon nitride layer 104 is exposed, wherein the silicon nitride layer 104 functions as a polishing stop layer.
Referring to FIG. 1E, the silicon nitride layer 104 is removed to expose the pad oxide layer 102. Thereafter, the pad oxide layer 102 is removed by a hydrofluoric acid solution. As a result, shallow trench isolation regions 118a and 118b are formed.
However, in the prior method, there is a problem of non-uniformity owing to the different densities and sizes of the trenches 110 and 112. Furthermore, it is necessary to over-polish the insulator 116 to ensure that the insulator 116 cannot remain on the silicon nitride at all. This results in a first dent 130 created on the isolation region 118b, known as a dishing effect. Apart from the first dent 130, second dents 140 are formed at the top corners 120 during wet etching for removing the pad oxide layer 102 by a hydrofluoric acid solution, causing a kink effect. The kink effect not only decrease the threshold voltage of devices, but also cause a leakage current on the devices because corner parasitic MOSFETs relative to active regions are formed.